The LT7211D is a high performance DP1.2 to LVDS chip for VR/Display application.
For DP1.2 input, LT7211D can be configured as 1,2,4 lane, also support lane swap function. Adaptive equalization makes it suitable for long cable application and the maximum bandwidth is up to 21.6Gbps
For LVDS output, LT7211D can be configured as single-port or dual-port. For 2D video stream, the same video stream can be mapped to two separated panel, for 3D video format, left side data can be sent to one panel, and right side data can be sent to another panel.
With sophisticated MCU and the Embedded Flash, LT7211D support EDID buffer, DP/eDP input detection and determine to enter into power saving mode automatically. When the receiver of LT7211D locks the input signal, MCU can read the recovered timing parameters by MSA registers to match the ASSR. The DPCD registers are accessible via system I2C when debugging the full link training. Once the fast link training used, system time will save at least 400ms.
• DP/eDP Receiver
• Single/Dual-Port LVDS Transmitter
• Docking Station